Methods of forming a semiconductor device having a metal gate electrode and associated devices

ABSTRACT

Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.10/780,244, filed Feb. 17, 2004, which claims priority to Korean PatentApplication No. 10-2003-0010403, filed Feb. 19, 2003, the contents ofwhich are hereby incorporated by reference as if recited in full herein.

FIELD OF THE INVENTION

The present invention relates to methods of forming semiconductordevices. More particularly, the present invention relates to methods offorming semiconductor devices having a metal gate electrode.

BACKGROUND OF THE INVENTION

As semiconductor devices become more highly integrated, the size of gatepatterns can be reduced which can change an electrical propertyassociated with the gate pattern. For example, where a metal silicide,such as tungsten silicide, is used as a gate pattern, resistance of thegate pattern can increase (sometimes relatively rapidly) as size of thegate pattern is reduced. Thus, in order to adjust for the resistanceincrease caused by the reduced size gate pattern in a highly integratedsemiconductor device, a metal (such as tungsten) having a low resistancecan be used to offset the increased resistance caused by the reducedsize gate pattern. FIG. 1 is a cross-sectional diagram of asemiconductor device having a metal gate electrode according to theprior art. Referring to FIG. 1, a gate insulator 3, a gate polysiliconlayer 5, a barrier metal layer 7, a metal gate layer 9, and a cappinglayer 11 are sequentially formed and patterned to form a gate pattern13. In order to treat etch damage that can occur at the semiconductorsubstrate 1 and the gate polysilicon layer 5 during the patterningprocess, a thermal treatment process can be performed in an oxygenenvironment. At this time, as through a side surface of the metal gatelayer 9 while thermal treating under the oxygen environment, therebyforming an oxide layer “O” at a boundary between the metal barrier layer7 and the gate polysilicon layer 5. The oxide layer “O” may increaseresistance between the metal gate layer 9 and the gate polysilicon layer5. The increased resistance attributed to the oxide layer may result inone or more of an RC (time constant) delay, a lower operational speedand reliability in a semiconductor device.

SUMMARY

Embodiments of the invention provide methods of forming a semiconductordevice that can inhibit and/or prevent oxide formation between a metalgate layer and a gate polysilicon layer in a gate pattern.

Certain embodiments of the invention are directed to methods thatinclude forming an oxidation barrier layer covering at least a portionof a sidewall of a metal gate layer.

In particular embodiments, the method can include: sequentially forminga gate insulator, a gate polysilicon layer and a metal-containing layeron a semiconductor substrate. The metal-containing layer and the gatepolysilicon layer can be (sequentially) patterned to form a gate patterncomprising a stacked gate polysilicon pattern and a metal-gate(comprising a metal containing) pattern.

The method can include forming an oxidation barrier layer to cover atleast a portion of a sidewall of the metal-containing pattern. Inparticular embodiments, the oxidation barrier layer can be formed bychemical vapor deposition (CVD) and/or an atomic layer deposition (ALD).

In certain embodiments, the oxidation barrier layer can be deposited onsidewalls of the metal-containing layer with a greater thickness than onsurfaces of other layers due to a difference of chemical properties inthe material of the other layers, such as nucleation rate.

The oxidation barrier layer may comprise at least one of a metal, anoxide, a nitride or an oxynitride of the metal. In particularembodiments, the metal can be selected from the group consisting ofaluminum (Al), tantalum (Ta), titanium (Ti), hafnium (Hf) and gold (Au).

The oxidation barrier layer may be formed by selectively depositing ametal layer onto the sidewall(s) of the metal-gate pattern and thenoxidizing or nitrifying the deposited metal layer.

In particular embodiments, the oxidation barrier layer may compriseand/or be formed of aluminum oxide (Al₂O₃). For example, an aluminumlayer can be formed by using a CVD method and by supplyingmethylpyrrolidine alane (MPA) as a source gas and argon (Ar) of 100 sccmas a carrier gas at a temperature of between about 135˜145° C. and at apressure of between about 0.1˜1.1 Torr, and the aluminum layer can beoxidized under an oxygen-enriched environment or ambience.

According to another embodiment of the present invention, themetal-containing layer can be formed of a barrier metal layer and ametal gate layer that are sequentially stacked. The gate pattern cancomprise a gate polysilicon pattern, a barrier metal pattern and a metalgate pattern that are sequentially stacked. In particular embodiments,the metal gate layer can comprise tungsten. The barrier metal layer cancomprise tungsten nitride (WN) and/or titanium nitride (TiN). Theoxidation barrier layer may be selectively formed to cover substantiallyonly the metal gate pattern.

In certain embodiments, the methods can include forming a capping layeron the metal-containing layer. The capping layer can be patterned whenthe metal-containing layer and the gate polysilicon layer aresequentially patterned, thereby forming a gate pattern comprising a gatepolysilicon pattern, a metal-containing pattern and a capping patternthat are sequentially stacked.

In particular embodiments, a thermal treating process may besubsequently performed with respect to the semiconductor substratehaving the gate pattern with the oxidation barrier layer under anoxygen-enriched environment or ambience. The thermal treating processunder the oxygen environment may comprise supplying nitrogen as acarrier gas and supplying oxygen and hydrogen at a temperature ofbetween about 750˜950° C. with a ratio of oxygen/hydrogen of betweenabout 0.5˜1.3.

The oxidation barrier layer can inhibit oxygen penetration into themetal-containing layer so that there is a reduced and/or no formation ofa conventional oxide layer between the gate polysilicon pattern and themetal-containing pattern.

Still other embodiments are directed to methods of forming an integratedcircuit device having a metal gate electrode. The methods include: (a)forming a stacked gate pattern onto a target substrate, the gate patterncomprising a metal-gate pattern with opposing first and second surfacesand at least one sidewall; and (b) covering at least a portion of the atleast one sidewall of the metal-gate pattern with an oxidation barrierlayer.

In particular embodiments, the covering of the at least one sidewall ofthe metal-gate pattern comprises conformably covering substantially theentire outer surface of the sidewall(s) of the metal-gate pattern withthe oxidation barrier layer, and, as desired also covering the sidewallsof a barrier metal layer abutting the metal-gate pattern. The gatepattern can be formed so that it is substantially devoid of theoxidation barrier layer proximate to a sidewall of a respective gatepolysilicon pattern and a capping pattern.

In certain embodiments, the method can include thermally treating thegate pattern in an oxygen-enriched environment and inhibiting an oxidelayer from forming between the metal-barrier layer and the gatepolysilicon layer based on the configuration of the oxidation barrierlayer.

Other embodiments are directed to highly integrated semiconductorcircuit devices with metal gate electrodes and a reduced gate patternsize. The devices include: (a) a substrate; (b) a gate insulation layerdisposed over the substrate; (c) a plurality of spaced apart first gatepatterns stacked on the gate insulation layer above the substrate; (d) aplurality of corresponding spaced apart metal barrier patterns, arespective one stacked on each of the first gate patterns above the gateinsulation layer, the metal barrier patterns having at least oneupwardly extending sidewall; (e) a plurality of corresponding secondmetal gate patterns, a respective one stacked on each of the metalbarrier patterns above the first gate layer, the second metal gatepatterns having at least one upwardly extending sidewall; (f) aplurality of corresponding capping patterns, a respective one stacked oneach of the metal gate patterns above the metal barrier layer; and (g)an oxidation barrier layer conformably disposed over the metal barrierpattern sidewalls and the metal gate pattern sidewalls and beingsubstantially absent on sidewalls of the first gate patterns and thesidewalls of the capping layer pattern. The device is substantiallydevoid of an oxide layer extending at a boundary portion located betweenrespective metal barrier patterns and the corresponding first gatelayers. The oxidation barrier layer may have a thickness of betweenabout 5˜100 Å.

The foregoing and other objects and aspects of the present invention aredescribed in greater detail in the drawings herein and the specificationset forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional diagram of a prior art semiconductor devicehaving a metal gate electrode according to a conventional technology.

FIGS. 2A through 2C are cross-sectional diagrams sequentiallyillustrating exemplary operations and/or features for forming asemiconductor device having a metal gate electrode according toembodiments of the present invention.

DETAILED DESCRIPTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art.

In the drawings, the thickness of layers and regions may be exaggeratedfor clarity. It will be understood that when an element such as a layer,region or substrate is referred to as being “on” another element, it canbe directly on the other element or intervening elements may also bepresent.

Furthermore, relative terms, such as “beneath”, may be used herein todescribe one element's relationship to another elements as illustratedin the figures. It will be understood that relative terms are intendedto encompass different orientations of the device in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” other elementswould then be oriented “above” the other elements. The exemplary term“below”, can therefore, encompasses both an orientation of above andbelow.

It will be understood that although the terms first and second may beused herein to describe various regions, layers and/or sections, theseregions, layers and/or sections should not be limited by these terms.These terms are used to distinguish one region, layer or section fromanother region, layer or section. Thus, a first region, layer or sectiondiscussed below could be termed a second region, layer or section, andsimilarly, a second without departing from the teachings of the presentinvention. Like numbers refer to like elements throughout. In addition,although described herein with respect to semiconductor substrates anddevices, the present invention is directed to integrated circuits andcan include structures formed on other substrates.

FIGS. 2A through 2C are cross-sectional diagrams sequentiallyillustrating exemplary operations and/or features of forming asemiconductor device having a metal gate electrode according toembodiments of the present invention.

Referring to FIG. 2A, a gate insulator 110, a gate polysilicon layer120, a barrier metal layer 130, a metal gate layer 140 and a cappinglayer 150 can be sequentially stacked on a semiconductor substrate 100.The capping layer 150, the metal gate layer 140, the barrier metal layer130, and the gate polysilicon layer 120 can be (sequentially) patternedto form a gate pattern 155. As such, the gate pattern 155 can comprisestacked gate layers of corresponding patterns: a polysilicon pattern120, a barrier metal pattern 130, a metal gate pattern 140, and acapping pattern 150. The terms “layer” and “pattern” may be usedinterchangeably below to indicate the stacked components on thesemiconductor or other base substrate forming the gate pattern.

The gate insulator 110 may be formed by thermally oxidizing thesemiconductor substrate 100. The gate insulator 110 may be removedduring the patterning process to expose the semiconductor substrate 100,and subsequently formed again by a thermal treatment process. Thebarrier metal layer 130 may comprise tungsten nitride (WN) and/ortitanium nitride (TiN) that may be formed by a physical vapor deposition(PVD) or a chemical vapor deposition (CVD). The metal gate layer 140 maycomprise tungsten. The gate polysilicon layer 120 may comprisepolysilicon doped by impurities. The capping layer 150 may comprisesilicon oxide and/or silicon nitride.

Referring to FIG. 2B, an oxidation barrier layer 160 can be selectivelyformed on at least portions of the sidewalls of the metal gate pattern140 and on at least sidewalls (and typically at least a major portion ofthe primary upper and lower surfaces) of the barrier metal pattern 130.The oxidation barrier layer 160 can comprise metal as a constituent orthe constituent forming the oxidation barrier layer 160. In certainembodiments, the oxidation barrier layer 160 may be configured so as tocover substantially only the sidewalls of the metal gate pattern 140. Inother embodiments, the oxidation barrier layer 160 may be configured tocover only the lower portion of the sidewall(s) of the metal-gatepattern 140. The oxidation barrier layer 160 may be formed by anysuitable process, including but not limited to, chemical vapordeposition (CVD) or atomic layer deposition (ALD).

In particular embodiments, the oxidation barrier layer 160 can berelatively well-deposited (with a desired thickness) on sidewalls of themetal containing layers 130 and 140 but deposited in substantiallyreduced amounts, regions or thickness on surfaces of other layers,including adjacent layers or patterns 120 and 150 or more remote layer110. This differential or selectivity may be carried out usingdifferences in chemical properties of materials forming or coating thelayers, such as a nucleation rate.

In certain embodiments, in order to form the oxidation barrier layer160, a metal layer can be (selectively) deposited and the depositedmetal layer can be treated to form a metal oxide or metal nitridebarrier layer. The oxidation barrier layer 160 can be formed with athickness of between about 5˜100 Å.

In certain embodiments, such as when the oxidation barrier layer 160 isformed of aluminum oxide (Al₂O₃), an aluminum layer may be formedsubstantially only on sidewalls of the metal-containing layers 130 and140 by supplying methylpyrrolidine alane (MPA) as a source gas and argon(Ar) of as a carrier gas. Typically the Ar is supplied at about 100sccm, at a temperature of between about 135˜145° C. at a pressure ofbetween about 0.1˜1.1 Torr for about 5 seconds using a CVD method. Thealuminum layer can be naturally oxidized (at pressures at about and/orunder atmospheric pressure) to form the aluminum oxide for the oxidationbarrier layer 160. The aluminum layer may be selectively deposited onsurfaces of the metal containing layers 130, 140 but substantially noton other adjacent layers 110, 120 and 150.

Referring to FIG. 2C, a thermal treatment process can be performed withrespect to the semiconductor substrate 100 having the gate pattern 155with the oxidation barrier layer 160 under an oxygen-enrichedenvironment or ambience, thereby curing etch damage caused during thepatterning process (such as results in the pattern shown in FIG. 2A).The thermal treatment process under the oxygen-enriched environment orambience may be performed by supplying nitrogen (N₂) as a carrier gasand supplying hydrogen (H2) and oxygen (O₂) at a temperature of betweenabout 750˜950° C. In particular embodiments, the ratio ofoxygen/hydrogen may be between about 0.5˜1.3. The oxidation barrierlayer 160 can inhibit and/or prevent oxygen penetration into the metalgate pattern 140 to inhibit formation of an oxide layer between themetal gate pattern 140 and the gate polysilicon pattern 120. This, inturn, may improve reliability and/or operational speed in asemiconductor device, particularly a highly integrated semiconductordevice with reduced size gate patterns and/or metal gate electrodes.

Still referring to FIG. 2C, a low concentration impurity-doped region170 can be formed in the semiconductor substrate 100 at both sides ofthe gate pattern 155 by using the gate pattern 155 as anion-implantation mask. The low concentration impurity-doped region 170may be formed before forming the oxidation barrier layer 160 byimplanting impurities using the gate pattern 155 as an ion-implantationmask.

In operation, an insulation layer can be conformably formed at an entireupper surface above the semiconductor substrate 100, extending fromwhere the capping layer 150 or oxidation barrier layer 160 is formeddown to the gate insulation layer 110. The insulation layer can beanisotropically etched to form spacers 180 covering sidewalls of theindividually stacked layers 120, 130, 140, 150 that together form thesidewalls of the gate pattern 155. The insulation layer may comprisesilicon oxide or silicon nitride. A relatively high concentrationimpurity-doped region 190 can be formed in the semiconductor substrate100 by using the gate pattern 155 and the spacer 180 as ion-implantationmasks.

The gate pattern 155 may include a plurality of opposing sidewalls wherethe shape of the gate pattern 155 (when viewed from the top) isrectangular, square or other shape with more than one sidewall. However,the gate pattern 155 can include cylindrical, circular, or other shapeswith only one sidewall as well as other multi-sided configurations.Hence, in the claims, the term “sidewall(s)” is intended to encompassboth these sidewall configurations. In addition, although a respectiveone gate pattern 155 is illustrated, a highly integrated device cancomprise a plurality of the gate patterns 155, repeated on thesubstrate, as will be understood by one of skill in the art.

Accordingly, methods of forming semiconductor devices according toembodiments of the present invention can form an oxidation barrier layercovering at least a portion of the sidewall of the metal gate patternlayer, thereby inhibiting and/or preventing formation of an oxide layerbetween the metal gate pattern and the gate polysilicon pattern whichmay occur due to oxygen penetration in a subsequent process.

1. A highly integrated semiconductor circuit device with metal gateelectrodes and a reduced gate pattern size, comprising: a substrate; agate insulation layer disposed over the substrate; a plurality of spacedapart first gate layer patterns stacked on the gate insulation layerabove the substrate; a plurality of spaced apart barrier metal patterns,a respective one stacked on each of the first gate layer patterns abovethe gate insulation layer, the barrier metal patterns having at leastone upwardly extending sidewall; a plurality of metal gate patterns, arespective one stacked on each of the barrier metal patterns above thefirst gate layer pattern, the metal gate patterns having at least oneupwardly extending sidewall; a plurality of capping patterns, arespective one stacked on each of the metal gate patterns above thebarrier metal pattern; and an oxidation barrier layer conformablydisposed over the barrier metal pattern sidewalls and the metal gatepattern sidewalls and being substantially absent on sidewalls of thefirst gate layer patterns and the sidewalls of the capping layerpattern, wherein the device is substantially devoid of an oxide layerextending at a boundary portion located between respective barrier metalpatterns and the corresponding first gate layer patterns.
 2. A deviceaccording to claim 1, wherein the oxidation barrier layer has athickness of between about 5˜100 Å.
 3. A device according to claim 1,wherein the first gate layer patterns comprise gate polysiliconpatterns.
 4. A device according to claim 3, wherein the barrier metalpattern is directly stacked on the gate polysilcon pattern.
 5. A deviceaccording to claim 4, wherein the oxidation barrier layer comprisesmetal.
 6. A device according to claim 4, wherein the barrier and/ormetal gate patterns comprise tungsten.
 7. A device according to claim 1,wherein the barrier metal pattern comprises tungsten nitride (WN) ortitanium nitride (TiN).
 8. A semiconductor device with a metal gateelectrode, comprising: a semiconductor substrate; and a metal gateelectrode on the substrate, the metal gate electrode comprising astacked gate pattern comprising a gate polysilicon pattern, a barriermetal pattern on the gate polysilicon pattern, and a metal gate patternon the barrier metal pattern, wherein the device is substantially devoidof an oxide layer extending at a boundary portion located between thebarrier metal pattern and the gate polysilicon pattern.
 9. A deviceaccording to claim 8, wherein the barrier and/or metal gate patternscomprises tungsten.
 10. A device according to claim 8, wherein thebarrier metal layer comprises tungsten nitride (WN) or titanium nitride(TiN).
 11. A device according to claim 8, further comprising anoxidation barrier layer, wherein the oxidation barrier layer coverssubstantially only sidewall(s) of the metal gate pattern and the barriermetal pattern.
 12. A device according to claim 8, further comprising acapping layer on the metal gate pattern layer, wherein the capping layeris patterned thereby forming a device with the stacked gate pattern thatcomprises, in serial order, the gate polysilicon pattern, the metal-gatepattern and the capping pattern.
 13. A device according to claim 11,further comprising a spacer layer abutting a sidewall of the stackedgate pattern including a sidewall(s) of the polysilicon gate pattern, asidewall(s) of the oxidation barrier layer that resides over thesidewall(s) of the metal-gate pattern and the barrier metal pattern, anda sidewall(s) of the capping pattern.
 14. A device according to claim 8,further comprising an impurity-doped region in the semiconductorsubstrate at opposing sides of the stacked gate pattern.
 15. A deviceaccording to claim 11, wherein the oxidation layer comprises aluminum.16. A device according to claim 12, further comprising an oxidationbarrier layer, wherein the oxidation barrier layer covers substantiallyonly sidewall(s) of the metal gate pattern and the barrier metal patternsuch that the gate polysilicon pattern and the capping pattern aredevoid of the oxidation barrier layer.
 17. A semiconductor device with ametal gate electrode, comprising: a semiconductor substrate; a metalgate electrode on the substrate, the metal gate electrode comprising astacked gate pattern comprising a gate polysilicon pattern, a barriermetal pattern on the gate polysilicon pattern, and a metal gate patternon the barrier metal pattern, and a capping pattern on the metal gatepattern; and an oxidation barrier layer, wherein the oxidation barrierlayer covers substantially only sidewall(s) of the metal gate patternand the barrier metal pattern such that the gate polysilicon pattern andthe capping pattern are devoid of the oxidation barrier layer, whereinthe device is substantially devoid of an oxide layer extending at aboundary portion located between the barrier metal pattern and the gatepolysilicon pattern.
 18. A device according to claim 17, wherein theoxidation barrier layer has a thickness of between about 5˜100 Å.